Description:
As a Senior Digital Design Engineer, You Will
- Own the architecture and RTL development of digital control, communication and power management functionality
- Develop clean, synthesizable Verilog/SystemVerilog for low power mixed signal ASICs
- Build and maintain SystemVerilog verification environments, including assertions, coverage and self checking testbenches
- Work closely with analogue and system engineers to define interfaces, registers, clocks and calibration functionality
- Take designs through lint, CDC/RDC, synthesis and timing analysis, working closely with Physical Design where required
- Support FPGA based prototyping, pre silicon validation and eventual silicon bring up
- Contribute to design reviews, technical documentation and verification planning
Required Experience
- Strong commercial experience in digital ASIC design and RTL development
- Hands on experience with Verilog and/or SystemVerilog
- Experience taking digital designs from specification or architecture through RTL development and synthesis
- Good understanding of digital verification, including testbenches, assertions and functional coverage
- Experience with common front end quality checks such as lint, CDC/RDC and timing constraints
- Experience working on mixed signal chips is highly desirable