Senior Time Constraints Engineer

Description:

Seeking a Senior engineer to own timing constraints and synthesis for complex SoCs. You will develop and validate SDCs, drive synthesis for best PPA, perform LEC for RTL/netlist equivalence, and collaborate with design, architecture, IP, and physical teams to ensure robust timing closure and high-quality deliverables.

Responsibilities
 

• Develop and maintain block- and top-level timing constraints (SDC).
• Drive synthesis flows to meet PPA targets.
• Perform LEC to ensure RTL-to-gate equivalence.
• Define timing exceptions with design, architecture, and IP teams.
• Work with technology/PD teams to integrate node-specific constraints.
• Identify and communicate timing-critical paths to front-end teams.
• Support implementation and signoff teams in timing debug.
• Review final chip-level STA reports and contribute to signoff.
• Improve timing, synthesis, and LEC methodologies and automation.
   

Preferred Skills & Experience
 

• Deep SDC development experience.
• Hands-on synthesis (DC/FC/Genus).
• LEC proficiency (Formality/Conformal).
• Solid digital design and CDC understanding.
• Strong STA expertise (PrimeTime/Tempus).
• Strong scripting (Tcl/Python).
• Experience with ARM or 3rd-party IP integration.
• Prior tapeout and timing-closure experience.