Description:
This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within the prestigious PowerVR Hardware Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics, AI or connectivity processor and related IP.
You will:
- Be responsible for the delivery of all verification activities related to a GPU component or sub-system from early stages of verification planning to sign-off
- Create verification plans, develop and maintain UVM testbench components
- Track and report verification metrics and closure
- Participate in all stages of design specification definition providing feedback from the verification perspective
- Develop testbenches in UVM, write tests, sequences, functional coverage, assertions & verification plans.
- Be responsible for the definition, effort estimation and tracking of your own work
- Be able to influence and advance our GPU verification methodology
- Have the opportunity to lead, coach and mentor other members of the team
- Participate in design and verification reviews and recommend improvements
About You
Committed to making your customers, stakeholders and colleagues successful, you’re an excellent communicator, listener and collaborator who builds trusted partnerships by delivering what you say, when you say. You’re curious, solutions orientated and a world-class problem solver who constantly seeks opportunities to innovate and achieve the best possible outcome to the highest imaginable standard.
You'll have:
- Have a proven track record of developing verification environments for complex RTL designs
- Have excellent understanding of constrained-random verification methodology and challenges of verification closure
- Be confident in defining verification requirements, and work out the implementation approach and details of a testbench
- Be able to do root-cause analysis of complex issues and resolve them in a timely manner
- Have excellent knowledge of SystemVerilog and UVM
- Be able to develop new verification flows
- Have working knowledge of ASIC design methodologies, flows and tools
- Be able to plan, estimate and track your own work
- Experience working on multiple projects at one time
- The skill to be able to communicate technical issues both in written form and verbally
You might also have:
- Experience leading teams
- Graphics/GPU/CPU/SoC knowledge
- Experience in wider verification technologies, such formal property based verification and code mutation
- Skill scripting in Python, TCL, Perl, SystemC, C++ experience
- Understanding of functional safety standards such as ISO26262