Verification Manager

Description:

The Verification Manager role will be a balance of technical and management responsibilities, with the successful candidate remaining involved in engineering discussions, verification strategy and project delivery rather than becoming purely people-focused.

The team is also going through a period of development, giving the Verification Manager genuine scope to influence how the group operates, from verification methodology and processes through to team structure, culture and technical development.

You’ll work closely with engineering leadership and other stakeholders, helping define verification strategies, monitor project progress and identify areas where the team and its processes can be improved.

What They’re Looking For
 

• Experience managing or leading digital verification engineers
• Strong background in the verification of complex ICs
• Strong SystemVerilog and UVM experience, with knowledge of assertions and coverage-driven verification
• Experience developing verification strategies and using metrics such as code and functional coverage
• Ability to support, mentor and develop engineers at different levels of experience
• Strong debugging and problem-solving skills across RTL and verification environments
• A technical mindset with the ability to make decisions and solve complex problems