Efficiency Engineer

Description:

We are looking for an Efficiency Engineer to support the data-driven optimization, analysis and maintenance of Arm’s engineering platforms. This role will work as part of a team effort to improve system utilisation / efficiency / cost-performance and touch on forecasting accuracy and infrastructure strategy.

Working within the Productivity Engineering group, there will be a focus on metrics, automation, data-engineering and problem-solving where applicable to efficiency topics, in a metrics-first / data-driven-decisions environment. We expect this work to drive scalability and vendor strategy across HPC compute, cloud, Emulation and FPGA environments.

Responsibilities
 

• Platform Optimization and Systems Engineering: Contributing to improvements in HPC scheduling and infrastructure efficiency.
• Assist with performance benchmarking activities, to help support platform decisions.
• Observability and Performance Analysis: Developing dashboards and visualisations.
• Cost and Resource Optimisation: Analysing Cost and Usage Reports (CUR) and infrastructure metrics to support forecasting, budgeting, and optimization strategies for large-scale compute environments.
• Build and maintain scalable analytics frameworks to measure utilisation, capacity, and workload behaviour.
• Partner with engineering, operations, and finance teams to ensure data-driven decision making.
   

Required Skills and Experience :
 

• Background in distributed HPC, cloud environments, data engineering & analytics.
• Knowledge of EDA workflows and semiconductor engineering environments.
• Proficiency in Python and data analysis/ML frameworks.
• Ability to turn sophisticated data into clear, actionable strategy.
   

“Nice To Have” Skills and Experience :
 

• Experience with IBM Spectrum LSF or other job schedulers.
• Familiarity with NetApp or high-performance storage systems.
• Experience applying AI/ML to workload optimization or resource management.
• Experience building production-grade data pipelines.
• Exposure to FPGA and Emulation infrastructure.